Generally speaking, manufacturing processes of semiconductors include a wafer fabrication process, a wafer probing process, a wafer packaging process, and a wafer testing process. During the wafer fabrication process, a plurality of individual dies are formed on a single wafer. The electrical property of each die is tested by a testing device in the wafer probing process. After the wafer probing process is performed, each individual faulty die is found and typically marked with a color ink dot to be distinguished from a good die. However, the method of marking each faulty die with the color ink dot has many shortcomings. For example, the color ink may chemically damage or smudge other good dies, so that they are difficult to be distinguished from faulty dies. For this reason, many alternatives to record the result of the wafer test information have been developed to eliminate the aforementioned shortcomings. One typical method uses a computer to generate a wafer map, which records the result of the wafer test information. Typically, the wafer map shows the location of each faulty die and the type of manufacturing defects of the faulty die. The information may be printed in paper or transmitted to a monitor for further analyzing by a yield-analyzing engineer.
A conventional wafer map 10 generated by a computer as shown in FIG. 1 shows the yield condition with respect to a plurality of dies 12 on a single wafer 11 and the locations of the plurality of faulty dies 13 indicated by a variety of signals and colors.
Conventional techniques rely on an “eyeball” method, in which an experienced yield-analyzing engineer should manually examine each failure signature on wafer maps generated by a computer, and then make his best judgment to sort the wafers by the failure signatures. After sorting, the causes of the faulty dies on wafers may be further analyzed by an analytic device.
However, this conventional method has many limitations in practical applications. First, the yield-analyzing engineer must spend much time on examining each wafer map. Second, the yield-analyzing engineer must have sufficient knowledge and experiences about failure signatures of wafer maps so as to be qualified to do this task. Moreover, the further analyses of causes of faults are not done until the yield-analyzing engineer sorts the failure signatures of new coming wafers. Additionally, the manually operated method may have unavoidable artificial negligence.
In view of the foregoing, it is desirable to provide a method of automatically searching for the failure signatures of wafers to avoid the aforementioned shortcomings of the prior art.